| S1 | S2 | S3 | S4 | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
![]() | ![]() | ![]() | ![]() |
|||||||||||||||||
| DIP | 1 | 2 | 3 | 4 | 1 | 2 | 3 | 4 | 1 | 2 | 3 | 4 | 1 | 2 | 3 | 4 | ||||
| ON | • | • | • | • | • | |||||||||||||||
| OFF | • | • | • | • | • | • | • | • | • | • | • | |||||||||
| S1 | ||
|---|---|---|
| DIP | ON | OFF |
| 1 | GPIO DIP 0 low | GPIO DIP 0 high |
| 2 | GPIO DIP 1 low | GPIO DIP 1 high |
| 3 | GPIO DIP 2 low | GPIO DIP 2 high |
| 4 | XFI_ENSMB# low | XFI_ENSMB# high |
| S2 | ||
|---|---|---|
| DIP | ON | OFF |
| 1 | DIU – Display Interface | TDM Interface |
| 2 | TBD – depends on software of system controller on TQMT1042 | - |
| 3 | T1024 USB-Clock | T1042 USB-Clock |
| 4 | Serdes PLL1 clock = 156.25 MHz | Serdes PLL1 clock = 100 MHz |
| S3 | ||
|---|---|---|
| DIP | ON | OFF |
| 1 | Lane C: SGMII | Lane C: QSGMII |
| 2 | Lane E: miniPCIe | Lane E: Aurora |
| 3 | Lane G: miniPCIe | Lane G: SGMII or SATA |
| 4 | Lane G: SGMII | Lane G: SATA |
| S4 | ||
|---|---|---|
| DIP | ON | OFF |
| 1 | DVDD=3.3 V | DVDD=1.8 V |
| 2 | EVDD=3.3 V | EVDD=1.8 V |
| 3 | CVDD=3.3 V | CVDD=1.8 V |
| 4 | SDHC Boot | Other Boot source |