WORK IN PROGRESS
STKT104x DIP switch settings
Boot Configuration
Use DIP switches S1, S2, S3 and S4 on the STKT104x to configure one of the following boot devices.
SD card
| S1 | S2 | S3 | S4 | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
 |  |
|||||||||||||||||||
| DIP | 4 | 3 | 2 | 1 | 4 | 3 | 2 | 1 | 4 | 3 | 2 | 1 | 4 | 3 | 2 | 1 | ||||
| OFF | • | • | • | |||||||||||||||||
| ON | • | • | • | • | • | |||||||||||||||
NOR Flash
| S1 | S2 | S3 | S4 | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
 |  |
|||||||||||||||||||
| DIP | 4 | 3 | 2 | 1 | 4 | 3 | 2 | 1 | 4 | 3 | 2 | 1 | 4 | 3 | 2 | 1 | ||||
| OFF | • | • | • | • | • | |||||||||||||||
| ON | • | • | • | |||||||||||||||||
TQMT1042 SerDes Configuration (0x88)
| S3 | S9 | |||||||
 |  |
|||||||
|---|---|---|---|---|---|---|---|---|
| DIP | 1 | 2 | 3 | 4 | 1 | 2 | ||
| ON | • | |||||||
| OFF | • | • | • | • | • | |||
| Ethernet interface assigment | |||
|---|---|---|---|
| X30 | X37 | ||
| not used | fm1-mac0 | fm1-mac3 | * |
| fm1-mac2 | not used | fm1-mac4 | fmc-mac1 |
TQMT1040 SerDes Configuration (0x66)
| S3 | S9 | |||||||
 |  |
|||||||
|---|---|---|---|---|---|---|---|---|
| DIP | 1 | 2 | 3 | 4 | 1 | 2 | ||
| ON | • | |||||||
| OFF | • | • | • | • | • | |||
| Ethernet interface assigment | |||
|---|---|---|---|
| X30 | X37 | ||
| * | * | fm1-mac3 | not used |
| * | * | fm1-mac4 | not used |
* Connected to Ethernet switch on STKT104x (with RCW TQMT1040_SERDES66 and DIP switch configuration for SERDES66)
Dip Switches S1 - S4
| S1 | ||
|---|---|---|
| DIP | ON | OFF |
| 1 | GPIO DIP 0 low | GPIO DIP 0 high |
| 2 | GPIO DIP 1 low | GPIO DIP 1 high |
| 3 | GPIO DIP 2 low | GPIO DIP 2 high |
| 4 | XFI_ENSMB# low | XFI_ENSMB# high |
| S2 | ||
|---|---|---|
| DIP | ON | OFF |
| 1 | TDM Interface | DIU – Display Interface |
| 2 | SD Card / eMMC Boot | NOR Flash Boot |
| 3 | T1024 USB-Clock (CPU Ball D3) | T1042 USB-Clock (CPU Ball F8) |
| 4 | Serdes PLL1 clock = 156.25 MHz | Serdes PLL1 clock = 100 MHz |
| S3 | ||
|---|---|---|
| DIP | ON | OFF |
| 1 | Lane C: SGMII | Lane C: QSGMII |
| 2 | Lane E: miniPCIe | Lane E: Aurora |
| 3 | Lane G: miniPCIe | Lane G: SGMII or SATA |
| 4 | Lane G: SGMII | Lane G: SATA |
| S4 | ||
|---|---|---|
| DIP | ON | OFF |
| 1 | DVDD=3.3 V | DVDD=1.8 V |
| 2 | EVDD=3.3 V | EVDD=1.8 V |
| 3 | CVDD=3.3 V | CVDD=1.8 V |
| 4 | SDHC Boot | eMMC |
| S9 | ||
|---|---|---|
| DIP | ON | OFF |
| 1 | D21 REFCLK 156.25 MHz | D21 REFCLK 125 MHz |
| 2 | D21 Config QSGMII to Copper | D21 Config SGMII to Copper |