Table of Contents

Embedded module TQMxE39C1 Documentation



BIOS Overview

BIOS Overview

BIOS Revision BIOS Version TXE Firmware Version PCI Configurations BIOS Binary
Rev. 0107 5.12.30.33.20 3.1.90.2629 4×1 PCIe Lanes TQMxE39C_5.12.30.33.20.bin
Rev. 0105 5.12.30.28.13 3.1.65.2317 4×1 PCIe Lanes TQMxE39C_5.12.30.28.13.bin
Rev. 0104 5.12.30.21.12 3.1.50.2238 4×1 PCIe Lanes TQMxE39C_5.12.30.21.12.bin
1×4 PCIe Lanes TQMxE39C_5.12.30.21.12_PCIe_1x4.bin
1×2 + 2×1 PCIe Lanes TQMxE39C_5.12.30.21.12_PCIe_1x22x1.bin
Rev. 0103 5.12.30.21.09 3.1.50.2238 4×1 PCIe Lanes TQMxE39C_5.12.30.21.09.bin
1×4 PCIe Lanes TQMxE39C_5.12.30.21.09_PCIe_1x4.bin
1×2 + 2×1 PCIe Lanes TQMxE39C_5.12.30.21.09_PCIe_1x22x1.bin
Rev. 0102 5.12.30.21.08 3.1.50.2238 4×1 PCIe Lanes TQMxE39C_5.12.30.21.08.bin
1×4 PCIe Lanes TQMxE39C_5.12.30.21.08_PCIe_1x4.bin
1×2 + 2×1 PCIe Lanes TQMxE39C_5.12.30.21.08_PCIe_1x22x1.bin
Rev. 0101 5.12.09.16.04 3.0.20.1139 4×1 PCIe Lanes TQMxE39C_5.12.09.16.04.bin
1×4 PCIe Lanes TQMxE39C_5.12.09.16.04_PCIe_1x4.bin
1×2 + 2×1 PCIe Lanes TQMxE39C_5.12.09.16.04_PCIe_1x22x1.bin
Rev. 0100 5.11.47.13.01 3.0.11.1131 4×1 PCIe Lanes TQMxE39C1_5.11.47.13.01.bin

Changelog

Changelog

5.12.30.33.20

Insyde Core Update to tag 05.12.30.0033 plus additional IB trunks

  • Close following security vulnerabilities
    • CVE-2021-41839
    • CVE-2021-41841
    • CVE-2021-41840
    • CVE-2020-27339
    • CVE-2021-42060
    • CVE-2021-42113
    • CVE-2021-43522
    • CVE-2022-24069
    • CVE-2021-43615
    • CVE-2021-41837
    • CVE-2021-41838
    • CVE-2021-33627
    • CVE-2021-45971
    • CVE-2021-33626
    • CVE-2021-45970
    • CVE-2021-45969
    • CVE-2022-24030
    • CVE-2021-42554
    • CVE-2021-33625
    • CVE-2022-24031
    • CVE-2021-43323
    • CVE-2021-42059

- Change Default configuration 

+ DTS     <Disabled>

- Disable Super I/Os not used 

+ SioNpcE285

- Define USB Overcurrent pins

5.12.30.28.13

  • core update to tag_05.12.30.0028
    • Update SIC code to 1.1.1
    • improve realtime behavior

5.12.30.21.12

  • Adapt setup menu
    • Unhide power limits
    • Unhide DCI Enable
  • USB Device functionality
    • Unhide XDCI Support
    • Adapt Strings of xDCI for better understanding

5.12.30.21.09

  • Add Smart Battery Switch in BIOS Menu
  • Support F1-Stepping
  • Update PMC Version
  • Update Microcode
  • Update SIC Version
  • Update GPIO configuration to fix SD-Card functionality

5.12.30.21.08

  • core update to tag 05.12.30.0021
    • close security gap spectre variant 2, 3a and 4
    • fix 'State after G3' issue
    • fix USB 3.0 not working
  • adapt setup default configuration
    • USB Per-Port Control > enabled
  • adapt setup menu
    • unhide “OS Reset Select”
    • hide “BIOS Boot Source” information
  • fix H2OUVE default bug of LFP configuration
  • integrate MRC patch to fix ECC issue (stop booting with postcode 30)
  • use old InsydeCrPkg to fix boot stop with postcode 0x0C84 or 0x004D
  • fix not working SPI flash GD 25LQ128D
  • support coinless Apl-I BIOS
  • support Smart Battery

5.12.09.16.04

  • update to Insyde BIOS 05.12.09.0016
  • update setup defaults (Memory Scrambler > disabled)
  • adapt setup menu: hide more menus
  • fix not working Single Power Button Event
  • Implement fan scaling configuration
  • update SioNct7802y package supporting Form Browser
  • support form browser
  • make IRQ 5, 6 and 7 adjustable
  • fix not booting from external flash
  • GPIO configuration were adapted to increase lifetime of pins
  • fix not working Console Redirection
  • add UEFI-LVDS and update driver

5.11.47.13.01

  • adapt Child Device list in GOP mode
  • switch from TQMxE39M to TQMxE39C1
  • adapt Setup Main Page and CPLD to TQMxE39C1
  • enable EFP2 per default
  • adapt GOP configuration to TQMxE39C1
  • adapt VBIOS configuration to TQMxE39C1
  • fix not working passive display adapter
  • Unhide EFP2 per default
  • update setup defaults (USB Per-Port Control > enabled)
  • add verb table for ALC262 codec
  • fix not booting from external SPI-flash


On-board I2C devices

On-board I2C devices

Bus Destination Function Address 8-bit Address 7-bit
SMBUS SODIMM Thermal Sensor (CH-A) 0x301) 0x18
SODIMM SPD EEPROM (CH-A) 0xA0 0x50
SODIMM Thermal Sensor (CH-B) 0x342) 0x1A
SODIMM SPD EEPROM (CH-B) 0xA4 0x52
NCT7802 Hardware Monitor 0x58 0x2C
FPGA non non non
COMe Con. any N/A3) N/A
I2C COMe 24LC32 COMe EEPROM 0xA0 0x50
COMe Con. any N/A4) N/A
I2C intern PTN3460IBS-F2 LVDS-Bridge 0xC0 0x60


1) , 2)
Availability depends on SODIMM vendor
3) , 4)
Availability and addresses depend on customer